Datapath Design using Verilog

The webinar on Datapath Designing using VERILOG is organized by the Center for Signal Processing and Communication Systems(CSPCS) on 12th June 2020 by Dr.P.Saravanan.

About speaker
Dr.P. Saravanan(Associate professor, PSG college of engineering)has completed his Ph.D. at Anna university in hardware security. He has got his master’s degree from PSG college of technology in VLSI design. His research interest areas are VLSI design, testing, verification, and hardware security and are skilled in quantum computing, Verilog and System Verilog, embedded processing with FPGAs, and many others.

Introduction and webinar
The webinar started at 11:00 am and lasted up to 12:15 pm. The speaker Dr.P. Saravanan sir started the webinar after a welcome by the CSPCS student coordinator. Around 100 students registered themselves for this program.
The program started with giving an introduction to the basics of hardware and its components. It further continued by describing types of ASICs and standard cell structure. Detailed information about FPGA architecture, Design style comparisons is provided.

Difference between FPGA and ASICs, FPGAs that are commercially available, Shannon’s decomposition, logic array block, processing systems, FPGA applications and its uses, HDL vs Software languages, top-down approach, Linux infrastructure and may more such interesting and related topics are explained in detail in a clear, interesting and easier manner.

The webinar turned much more interesting when the Verilog module was explained. Participants are taught to design a datapath using this Verilog model.

Participants are provided with the basic knowledge that is required to understand these concepts which made them learn something new providing the best learning experience. The program continued with an interactive Q&A session and all the participants found this program highly interesting and informative.

The Ending Salutations
The program ended with a vote of thanks by the CSPCS student
coordinator.